Complementary metal oxide semiconductor (CMOS) integrated circuits often perform complex multistep operations having critical timing. A reference clock can provide at most two precision edges; e.g. the leading and trailing edges. Multistep operations that must be triggered at other points in the clock period therefore cannot use the reference clock as a trigger source.
The synchronous delay line (SDL)is a MOS circuit function which provides timing edges at precise, evenly-spaced intervals, and is insensitive to variations in processing, Vcc, or temperature. These timing edges enable the triggering of logic operations practically at any time with high resolution and precision.
A prior art synchronous delay line is shown in FIG. 1. This SDL was disclosed in U.S. Pat. No. 4,994,695, entitled "Synchronous Delay Line with Quadrature Clock Phases", which is assigned to the assignee of the present invention. SDL 20 is comprised of a phase generator 21, a plurality of series coupled voltage-controlled delay (VCD) stages 22, and a sample-and-hold circuit 23. SDL 20 includes 8 VCD stages, with each VCD stage 22 providing an output, or tap, of SDL 20.
FIG. 2 illustrates prior art phase generator 21, which includes a D-type master latch, a D-type slave latch, an edge-triggered D-type flip-flop, and several buffers. Phase generator 21 accepts the reference clock signal CLK and divides it by two to generate two pairs of complementary clock phases, PHI.sub.1 /PHI.sub.2 and PHIQ.sub.1 /PHIQ.sub.2. Two trigger signals PA.sub.0 and PB.sub.0 are also generated by the phase generator 21. PA.sub.0 and PB.sub.0 are also derived from the reference clock signal CLK and are complementary to each other. PA.sub.0 and PB.sub.0 are coupled to the first VCD stage 22 as trigger inputs. Although clock phases PHI.sub.1 and PHI.sub.2 could serve as trigger inputs, separate trigger inputs are generated due to the heavy capacitive loads that PHI.sub.1 and PHI.sub.2 typically drive.
The latches and flip-flops of FIG. 2 may be implemented in different ways, each one having advantages. FIG. 3A illustrates typical prior art latch that samples its D-input when CLK is low. FIG. 3B illustrates a typical prior art phase that samples its D-input when CLK is high. If the rising edge of CLK is used as the reference edge then the latch of FIG. 3A is used as the master latch and the latch of FIG. 3B is used as the slave latch in the circuit of FIG. 2. On the other hand, if the falling edge of CLK is designated as the reference edge then the roles of the latches of FIG. 3A and FIG. 3B are reversed.
FIG. 4 illustrates the waveforms generated by prior art phase generator 21 when using the latches of FIG. 3 and the rising edge of CLK as the reference. FIG. 4 reveals several characteristics of the prior art phase generator. First, PHI.sub.1 is logically the same as PA.sub.0 ; they both divide the frequency of CLK by two. Similarly, PHI.sub.2 and PB.sub.0 are logically identical to each other and are logical complements of PHI.sub.1 and PA.sub.0. Second, the rising edge of PHIQ.sub.1 always leads the falling edge of PHIQ.sub.2, just as the rising edge of PHIQ.sub.2 always leads the falling edge of PHIQ.sub.1. This characteristic arises from the latch of FIG. 3A, which serves as the master latch. In this circuit, Q can go low only after Q goes high, and conversely, Q can go low only after Q goes high. Third, the falling edge of PHI.sub.1 always leads the rising edge of PHI.sub.2, while the falling edge of PHI.sub.2 always leads the rising edge of PHI.sub.1. These same relationships hold for PA.sub.0 and PB.sub.0. The structure of the latch of FIG. 3B, which serves as the slave latch, gives rise to this characteristic. Q can go high only after Q goes low, and conversely, Q can go high only after Q goes low.
These characteristics cause an inherent skew between trigger signals PA.sub.0 and PB.sub.0 that cannot be eliminated.
The outputs of each VCD stage 22, designated as PA.sub.n and PB.sub.n, are coupled as trigger inputs to subsequent stages.
A prior art VCD 22, or delay element 22, is shown in FIG. 5. The delay element 22 includes two cross-coupled NAND gates, A and B. Due to the design of delay element 22, only one of the complementary trigger inputs, PA.sub.0 or PB.sub.0, will propagate a signal, or wave, down SDL 20. The SDL 20 is triggered when either of the trigger inputs, PA.sub.0 or PB.sub.0, transistions from high to low. The route followed by the propagating wave is different in each clock phase. FIG. 6 indicates the route followed by the wave generated when PA.sub.0 goes low and PB.sub.0 goes high. FIG. 7 shows the route followed by the wave generated when PA.sub.0 goes high and PB.sub.0 goes low.
Clearly, only the low-going trigger input triggers propagation. The other trigger input, the high-going one, simply enables wave propagation. The timing skew between trigger inputs PA.sub.0 and PB.sub.0 is not critical: the enabling input may switch within a large window surrounding the switching of the triggering trigger input.
The delay between taps of SDL 20 is equal to the delay through the two gates, A and B, in each delay element 22. On alternate clocks, the propagation path of the wave through each delay element is reversed so that the delay through an arbitrary delay element is t.sub.dh (A)+t.sub.dl (B) for one clock, and t.sub.dl (A)+t.sub.dh (B) for the next clock, where t.sub.dh is the gate high-going delay time, and t.sub.dl is the gate low-going delay time. Because the gates are matched in all respects, including in layout, the delay through the gates on alternate clocks is identical. Consequently, the delay through the delay element 22 on alternate clocks is identical.
The delay control voltage V.sub.CTRL controls the delay time of each delay element 22 and, consequently, the SDL end-to-end delay. As V.sub.CTRL increases so does the SDL end-to-end delay. Through negative feedback, V.sub.CTRL stabilizes at a value which causes the SDL end-to-end delay to just equal the clock period TP. Thus, the higher the operating frequency, the lower the steady-state value of V.sub.CTRL.
The resolution of SDL 20 is limited by the tap-to-tap delay t.sub.del. The delay is given by t.sub.del =TP/N, where N is the number of SDL taps. The number of taps is determined by the highest operating frequency of the integrated circuit in which the SDL is implemented. At the highest operating frequency V.sub.CTRL is approximately OV because the SDL operates at the highest frequency with minimum delay. Thus, the maximum number of SDL taps that can be implemented is determined by the SDL end-to-end delay at the maximum frequency. Because each delay element contributes one t.sub.dh and one t.sub.dl of delay, the maximum number of taps N.sub.max is given by EQU N.sub.max =TP.sub.min /(t.sub.dh,min +t.sub.dl,min)
where:
TP.sub.min is the clock period at the maximum frequency; and PA1 t.sub.dh,min and t.sub.dl,min are the minimum values of t.sub.dh and t.sub.dl, respectively, which are obtained when V.sub.CTRL is approximately OV.
In other words, the maximum number of taps that can be implemented in a prior art SDL, which is synonymous with the maximum resolution obtainable from a prior art SDL, is limited by the fact that the delay contributed by each delay element is two gate delays. This is less than optimum resolution for certain high performance multi-step operations.